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89 lines
1.8 KiB
89 lines
1.8 KiB
# RISC combined instruction set
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goal: a semi-efficient insatruction set that offers few instructions that offer
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the combined functions of conventional risc instuctions.
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as such most instructions could be pipelined, I don't know how to feel about that
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# Memory Operations
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when accessing memory trough an address a consecutive pair of registers is used,
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each consecutive pair of registers is given a name, for brevity a pair is
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always referred to as `A`. The possible pairs are:
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- A = R1:R0
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- B = R3:R2
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- C = R5:R4
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- D = R7:R6
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- E = R9:R8
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- F = R11:R10
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- G = R13:R12
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- H = R15:R14
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- I = R17:R16
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- J = R19:R18
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- K = R21:R20
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- L = R23:R22
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- M = R25:R24
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- N = R27:R26
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- O = R29:R28
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- P = R31:R30
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## LD load value into register
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normal loading
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syntax: `LD Rd, A`
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action: `Rd = [A]`
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post increment/decrement
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syntax: `LD Rd, A+q`
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action: `Rd = [A]; A += q`
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pre increment/decrement
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syntax: `LD Rd, q+A`
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action: `A += q; Rd = [A]`
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## LDI load immediate into register
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syntax: `LDI Rd, imm`
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action: `Rd = imm`
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## LDIL load long immediate into register
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syntax: `LDIL Rd, imm32`
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action: `Rd = imm32`
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## ST store value from register
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normal storing
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syntax: `ST A, Rd`
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action: `[A] = Rd`
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post increment/decrement
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syntax: `ST A+q, Rd`
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action: `[A] = Rd; A += q`
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pre increment/decrement
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syntax: `ST q+A, Rd`
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action: `A += q; [A] = Rd`
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## STI store immediate into memory
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normal store
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syntax: `STI A, imm`
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action: `[A] = imm`
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post increment/decrement
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syntax: `STI A+q, imm`
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action: `[A] = imm; A += q`
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pre increment/decrement
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syntax: `STI q+A, imm`
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action: `A += q; [A] = imm`
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## STIL store long immediate into memory
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normal store
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syntax: `STIL A, imm32`
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action: `[A] = imm32`
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post increment/decrement
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syntax: `STIL A+q, imm32`
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action: `[A] = imm32; A += q`
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pre increment/decrement
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syntax: `STIL q+A, imm32`
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action: `A += q; [A] = imm32`
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