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******************************************************************************
* Simulation model of IRS10752L Level 1 for SIMetrix version 8.3g or higher
* Version: 01.02 (Revision: 551)
* (C) Copyright 2020 Infineon Technologies. All rights reserved.
*
******************************************************************************
* Model performance :
* - Static Electrical Characteristics and Dynamic Electrical Characteristics
* are modeled with the typical values from the datasheet.
* - Temperature effects are not modeled
*
* The following features have been modeled :
* - Switching Characteristics such as propagation delay, peak currents
* - Undervoltage lockout
*
******************************************************************************
* PINS:
* --------------------------------------------------------------------------
* | NAME | DESCRIPTION
* --------------------------------------------------------------------------
* | HO | High side gate drive output
* --------------------------------------------------------------------------
* | COM | Low side return
* --------------------------------------------------------------------------
* | IN | Logic input for gate driver output (HO), in phase with HO
* --------------------------------------------------------------------------
* | VCC | Low-side and logic supply voltage
* --------------------------------------------------------------------------
* | VB | High side floating supply
* --------------------------------------------------------------------------
* | VS | High side floating supply return
* --------------------------------------------------------------------------
*
******************************************************************************
* DISCLAIMER
*
* INFINEON’S MODEL TERMS OF USE
*
* BY DOWNLOADING AND/OR USING THIS INFINEON MODEL (“MODEL”), THE USER
* (INCLUDING YOU) AGREES TO BE BOUND BY THE TERMS OF USE HERE STATED. IF USER
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* WAS DOWNLOADED ALREADY).
*
* 1. SCOPE OF USE
* 1.1 Any use of this Model provided by Infineon Technologies AG is subject
* to these Terms of Use.
* 1.2 This Model, provided by Infineon, does not fully represent all of the
* specifications and operating characteristics of the product to which
* this Model relates.
* 1.3 This Model only describes the characteristics of a typical product.
* In all cases, the current data sheet information for a given product
* is the final design guideline and the only actual performance
* specification. Although this Model can be a useful tool to evaluate
* the product performance, it cannot simulate the exact product performance
* under all conditions and it is also not intended to replace
* bread-boarding for final verification.
*
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******************************************************************************
.SUBCKT IRS10752L HO COM IN VCC VB VS
R_HIN IN COM 1E12
C_HIN IN COM 1F
R_HO HO COM 1E12
C_HO HO COM 1F
R_VB VB COM 1E12
C_VB VB COM 1F
R_VS VS COM 1E12
C_VS VS COM 1F
R_LO LO COM 1E12
C_OUT LO COM 1F
E_LIN LIN COM VALUE={0}
R_VCC VCC COM 1E12
C_VCC VCC COM 1F
E_SD SD COM VALUE={5}
R_DT DT COM 1
C_DT DT COM 1P
X_GD_TEMPLATE LO HO COM LIN IN VCC VB VS SD DT IRS10752L_GD_TEMPLATE
.ENDS IRS10752L
.SUBCKT IRS10752L_GD_TEMPLATE LO HO COM LIN HIN VCC VB VS SD DT PARAMS: HB_EN=0 SHT_EN=0 P_OFFSET_DT=7.5E-08 P_SLOPE_DT=-0.0 P_SD_D=
+ 2.5714285714285715E-08 P_TH_SD_UP=2.1 P_TH_SD_DW=0.9 P_C_TPD=4.8914E-08 P_TH_TPD=0.4238339093 P_C_PW_MIN=1E-10 P_TH_HIN_OFF=1
+ P_TH_LIN_OFF=0.9 P_TH_HIN_ON=2 P_TH_LIN_ON=2.1 P_R_HIN_CL=749999.9999999999 P_R_LIN_CL=94285.71428571429 P_C_GATE=1.2E-11
+ P_RBOND_NMOS=0.01 P_RBOND_PMOS=0.01 P_LO_VGS_NMOS=3.0 P_LO_VGS_PMOS=3.22 P_LPMOS_LAMDA=0.53 P_LPMOS_KP=1.5E-05 P_LNMOS_LAMDA=0.28
+ P_LNMOS_KP=6.4E-05 P_HO_VGS_NMOS=8.14 P_HO_VGS_PMOS=8.32 P_HPMOS_LAMDA=0.241 P_HPMOS_KP=3E-06 P_HNMOS_LAMDA=0.041 P_HNMOS_KP=9E-6
+ P_VCC_UVH=9 P_VCC_UVL=8 P_VB_UVL=8 P_VB_UVH=9 P_R_UV_D_H=14285.714285714286 P_R_UV_D_L=14285.714285714286 P_VCC_MIN=8 P_IQ_VCC=
+ 0.0001 P_VB_MIN=8 P_IQ_VB=8E-05 P_V_LEAK=100 P_I_LEAK=2.5E-05 P_R_BSD=52 P_N_BSD=1.2294559113268089 P_IS_BSD=1E-17
R_HIN_CLAMP HIN COM {P_R_HIN_CL}
X_HIN_VCC_D HIN VCC IRS10752L_ESD_DIO PARAMS: P_V_BV=1 P_I_BV=1M
X_COM_HIN_D COM HIN IRS10752L_ESD_DIO PARAMS: P_V_BV=1 P_I_BV=1M
X_SD_VCC_D SD VCC IRS10752L_ESD_DIO PARAMS: P_V_BV=1 P_I_BV=1M
X_COM_SD_D COM SD IRS10752L_ESD_DIO PARAMS: P_V_BV=1 P_I_BV=1M
X_CL_VCC VCC COM IRS10752L_CL_DIO PARAMS: P_V_BV=20.2 P_I_BV=5M
X_CL_VB VB VS IRS10752L_CL_DIO PARAMS: P_V_BV=20.2 P_I_BV=5M
X_INPUT_STAGE LIN_DD HIN_DD SD_DD LIN HIN SD COM VCC VS VB IRS10752L_INPUT_STAGE PARAMS: P_SD_D={P_SD_D} P_TH_SD_UP={P_TH_SD_UP}
+ P_TH_SD_DW={P_TH_SD_DW} P_C_TPD={P_C_TPD} P_TH_TPD={P_TH_TPD} P_C_PW_MIN={P_C_PW_MIN} P_TH_HIN_OFF={P_TH_HIN_OFF} P_TH_LIN_OFF=
+ {P_TH_LIN_OFF} P_TH_HIN_ON={P_TH_HIN_ON} P_TH_LIN_ON={P_TH_LIN_ON}
X_DEADTIME LIN_DT_DIG HIN_DT_DIG LIN_DD HIN_DD DT VCC COM VCC_UV IRS10752L_DEADTIME PARAMS: P_SLOPE_DT={P_SLOPE_DT} P_OFFSET_DT=
+ {P_OFFSET_DT} HB_EN={HB_EN} SHT_EN = {SHT_EN}
X_HO_STAGE HO HIN_DT_DIG VCC_UV VB_UV SD_DD VB VS IRS10752L_HO_STAGE PARAMS: P_RBOND_PMOS={P_RBOND_PMOS} P_RBOND_NMOS=
+ {P_RBOND_NMOS} P_C_GATE={P_C_GATE} P_HO_VGS_PMOS={P_HO_VGS_PMOS} P_HPMOS_LAMDA={P_HPMOS_LAMDA} P_HPMOS_KP={P_HPMOS_KP}
+ P_HO_VGS_NMOS={P_HO_VGS_NMOS} P_HNMOS_LAMDA={P_HNMOS_LAMDA} P_HNMOS_KP={P_HNMOS_KP}
X_LO_STAGE LO LIN_DT_DIG VCC_UV SD_DD VCC COM IRS10752L_LO_STAGE PARAMS: P_RBOND_PMOS={P_RBOND_PMOS} P_RBOND_NMOS={P_RBOND_NMOS}
+ P_C_GATE={P_C_GATE} P_LO_VGS_PMOS={P_LO_VGS_PMOS} P_LPMOS_LAMDA={P_LPMOS_LAMDA} P_LPMOS_KP={P_LPMOS_KP} P_LO_VGS_NMOS=
+ {P_LO_VGS_NMOS} P_LNMOS_LAMDA={P_LNMOS_LAMDA} P_LNMOS_KP={P_LNMOS_KP}
X_UV_DETECT VCC_UV VB_UV VCC VB COM VS IRS10752L_UV_DETECT PARAMS: P_VB_UVL={P_VB_UVL} P_VB_UVH={P_VB_UVH} P_R_UV_D_H={P_R_UV_D_H}
+ P_VCC_UVL={P_VCC_UVL} P_VCC_UVH={P_VCC_UVH} P_R_UV_D_L={P_R_UV_D_L}
X_CC_EMULATOR VCC COM VB VS IRS10752L_CC_EMULATOR PARAMS: P_VB_MIN={P_VB_MIN} P_VCC_MIN={P_VCC_MIN} P_IQ_VB={P_IQ_VB} P_IQ_VCC=
+ {P_IQ_VCC} P_I_LEAK={P_I_LEAK} P_V_LEAK={P_V_LEAK}
.ENDS IRS10752L_GD_TEMPLATE
.SUBCKT IRS10752L_INPUT_STAGE LIN_DD HIN_DD SD_DD LIN HIN SD COM VCC VS VB PARAMS: P_SD_D=5E-08 P_TH_SD_UP=2.1 P_TH_SD_DW=1.1
+ P_C_TPD=1.9E-07 P_TH_TPD=10E-9 P_TH_HIN_OFF=0.9 P_TH_LIN_OFF=0.9 P_TH_HIN_ON=2.1 P_TH_LIN_ON=2.1 P_C_PW_MIN=42E-9
X_SD_TH SD SD_DIG COM IRS10752L_STP_IDEAL PARAMS: P_TH_UP={P_TH_SD_UP} P_TH_DW={P_TH_SD_DW}
X_SD_DD SD_DIG SD_DD IRS10752L_RC_DELAY_10 PARAMS: P_C_DELAY = {P_SD_D}
X_HIN_TH HIN HIN_DIG COM IRS10752L_STP_IDEAL PARAMS: P_TH_UP={P_TH_HIN_ON} P_TH_DW={P_TH_HIN_OFF}
X_HIN_LPF HIN_DIG HIN_LPF_DIG IRS10752L_ADV_FILTER PARAMS: P_C_DELAY = {P_C_PW_MIN}
X_HIN_DD HIN_LPF_DIG HIN_DD IRS10752L_RC_DELAY_10 PARAMS: P_C_DELAY = {P_C_TPD} P_TH_TPD = {P_TH_TPD}
X_LIN_TH LIN LIN_DIG COM IRS10752L_STP_IDEAL PARAMS: P_TH_UP={P_TH_LIN_ON} P_TH_DW={P_TH_LIN_OFF}
X_LIN_LPF LIN_DIG LIN_LPF_DIG IRS10752L_ADV_FILTER PARAMS: P_C_DELAY = {P_C_PW_MIN}
X_LIN_DD LIN_LPF_DIG LIN_DD IRS10752L_RC_DELAY_10 PARAMS: P_C_DELAY = {P_C_TPD} P_TH_TPD = {P_TH_TPD}
.ENDS IRS10752L_INPUT_STAGE
.SUBCKT IRS10752L_DEADTIME LIN_DT_DIG HIN_DT_DIG LIN HIN DT VCC COM VCC_UV PARAMS: HB_EN=1 SHT_EN=0.0 P_SLOPE_DT=2.43236451E-05
+ P_OFFSET_DT=5.4E-07 P_I_DT=1E-06 P_C_DT=10P P_TH_UP=0.5
X_LIN_DT LIN LIN_DD IRS10752L_RC_DELAY_10 PARAMS: P_C_DELAY = 0.3N
X_HIN_DT HIN HIN_DD IRS10752L_RC_DELAY_10 PARAMS: P_C_DELAY = 0.1N
E_VCC_1V VCC_1V 0 VALUE={TABLE( V(VCC,COM) , 0,0 , 3,0 , 6,1 )}
G_DT VCC DT VALUE={TABLE( V(VCC,DT) , 0,0 , 10M,{P_I_DT} )}
E_HDT_PLS HIN_DT_PLS 0 VALUE={IF( ((V(HIN_DD) - V(LIN_DD)) > 0.1) | (V(HIN_DT_DIG) > 0.5) | ({HB_EN} < 0.5), 1.0 , 0.0 )}
E_HIN_DT HIN_DT_DIG 0 VALUE={IF( ( ((V(HIN_DT_PLS) > 0.5) & (V(LOFF) > {P_TH_UP})) | {HB_EN} < 0.5 ) & (V(HIN_DD) > 0.5 ) & V(
+ VCC_UV)>0.5 , 1.0 , 0.0 )}
E_LDT_PLS LIN_DT_PLS 0 VALUE={IF( ((V(LIN_DD) - V(HIN_DD)) > 0.1) | (V(LIN_DT_DIG) > 0.5) | ({HB_EN} < 0.5) , 1.0 , 0.0 )}
E_LIN_DT LIN_DT_DIG 0 VALUE={IF( ( ((V(LIN_DT_PLS) > 0.5) & (V(HOFF) > {P_TH_UP})) | {HB_EN} < 0.5 ) & (V(LIN_DD) > 0.5 ) , 1.0 ,
+ 0.0 )}
E_SHT_H SHT_H 0 VALUE={IF( {SHT_EN} > 0.5 , V(HIN_DD) , V(HIN_DT_DIG) )}
E_SHT_L SHT_L 0 VALUE={IF( {SHT_EN} > 0.5 , V(LIN_DD) , V(LIN_DT_DIG) )}
G_H_DT VCC_1V HOFF VALUE={TABLE( V(VCC_1V,HOFF) , 0,0 , 10M, I_DT( V(DT,COM) ) )}
C_H_DT HOFF 0 {P_C_DT}
R_H_DT HOFF 0 1E8
S_H_DT HOFF 0 SHT_H 0 IRS10752L_DT_SW
G_L_DT VCC_1V LOFF VALUE={TABLE( V(VCC_1V,LOFF) , 0,0 , 10M, I_DT( V(DT,COM) ) )}
C_L_DT LOFF 0 {P_C_DT}
R_L_DT LOFF 0 1E8
S_L_DT LOFF 0 SHT_L 0 IRS10752L_DT_SW
.FUNC I_DT(V_DT) {{P_C_DT} * {P_TH_UP} / ({P_SLOPE_DT}/{P_I_DT}*V_DT + {P_OFFSET_DT})}
.MODEL IRS10752L_DT_SW VSWITCH RON=1 ROFF=100MEG VON=0.8 VOFF=0.2
.ENDS IRS10752L_DEADTIME
.SUBCKT IRS10752L_HO_STAGE HO HIN_DT_DIG VCC_UV VB_UV SD_DD VB VS PARAMS: P_RBOND_NMOS=10M P_RBOND_PMOS=10M P_C_GATE=1E-12
+ P_HO_VGS_PMOS=6 P_HPMOS_LAMDA=0.06 P_HPMOS_KP=60U P_HO_VGS_NMOS=6 P_HNMOS_LAMDA=0.05 P_HNMOS_KP=100U
R_HIN_DT_DD HIN_DT_DIG HIN_DT_DD 100
C_HIN_DT_DD HIN_DT_DD 0 1N
E_HIN_PLS HIN_PLS 0 VALUE {IF( (V(HIN_DT_DIG) - V(HIN_DT_DD)) > 0.1 | ((V(HGATE_DIG) > 0.5) & V(HIN_DT_DIG)>0.5), 1.0,0.0 )}
E_HGATE_DIG HGATE_DIG 0 VALUE {IF( ( V(VB_UV) > 0.5 & V(HIN_PLS) > 0.5 & V(SD_DD) > 0.5 ) , 1.0,0.0 )}
R_HGATE HGATE_DIG HGATE 1
C_HGATE HGATE 0 {P_C_GATE}
E_HO_VGS_PMOS HO_VGS_PMOS 0 VALUE={TABLE(V(VB,VS), 10, 7.5, 15,9.5,20,11.7)}
E_HO_VGS_NMOS HO_VGS_NMOS 0 VALUE={TABLE(V(VB,VS), 10, 8.67, 15,10.14,20,11.61)}
E_HGATE_P VB HGATE_P VALUE {V(HGATE) * {P_HO_VGS_PMOS} * V(HGATE_DIG)}
E_HGATE_N HGATE_N VS VALUE {(1 - V(HGATE)) * {P_HO_VGS_NMOS} * (1 - V(HGATE_DIG))}
M_HO_PMOS HO HGATE_P VB VB IRS10752L_HO_PMOS
M_HO_NMOS HO HGATE_N VS VS IRS10752L_HO_NMOS
.MODEL IRS10752L_HO_PMOS PMOS (LEVEL=1 VTO=-1 CGSO=100P W=1M L=1U RB=1 RG=10 RS=10M RD={P_RBOND_PMOS} LAMBDA={P_HPMOS_LAMDA} KP=
+ {P_HPMOS_KP} )
.MODEL IRS10752L_HO_NMOS NMOS (LEVEL=1 VTO=1 CGSO=100P W=1M L=1U RB=1 RG=10 RS=10M RD={P_RBOND_NMOS} LAMBDA={P_HNMOS_LAMDA} KP=
+ {P_HNMOS_KP} )
.ENDS IRS10752L_HO_STAGE
.SUBCKT IRS10752L_LO_STAGE LO LIN_DT_DIG VCC_UV SD_DD VCC COM PARAMS: P_RBOND_NMOS=10M P_RBOND_PMOS=10M P_C_GATE=1E-12
+ P_LO_VGS_PMOS=6 P_LPMOS_LAMDA=0.06 P_LPMOS_KP=60U P_LO_VGS_NMOS=6 P_LNMOS_LAMDA=0.05 P_LNMOS_KP=100U
E_LGATE_DIG LGATE_DIG 0 VALUE {IF( (V(VCC_UV) > 0.5 & V(LIN_DT_DIG) > 0.5 & V(SD_DD) > 0.5 ), 1.0,0.0 )}
R_LGATE LGATE_DIG LGATE 1
C_LGATE LGATE 0 {P_C_GATE}
E_LGATE_P VCC LGATE_P VALUE {V(LGATE) * {P_LO_VGS_PMOS} * V(LGATE_DIG)}
E_LGATE_N LGATE_N COM VALUE {(1 - V(LGATE)) * {P_LO_VGS_NMOS} * (1 - V(LGATE_DIG))}
M_LO_PMOS LO LGATE_P VCC VCC IRS10752L_LO_PMOS
M_LO_NMOS LO LGATE_N COM COM IRS10752L_LO_NMOS
.MODEL IRS10752L_LO_PMOS PMOS (LEVEL=1 VTO=-1 CGSO=100P W=1M L=1U RB=1 RG=10 RS=10M RD={P_RBOND_PMOS} LAMBDA={P_LPMOS_LAMDA} KP=
+ {P_LPMOS_KP} )
.MODEL IRS10752L_LO_NMOS NMOS (LEVEL=1 VTO=1 CGSO=100P W=1M L=1U RB=1 RG=10 RS=10M RD={P_RBOND_NMOS} LAMBDA={P_LNMOS_LAMDA} KP=
+ {P_LNMOS_KP} )
.ENDS IRS10752L_LO_STAGE
.SUBCKT IRS10752L_UV_DETECT VCC_UV VB_UV VCC VB COM VS PARAMS: P_VB_UVL=7 P_VB_UVH=8 P_R_UV_D_H=142857 P_VCC_UVL=8 P_VCC_UVH=9
+ P_R_UV_D_L=71428
X_VB_UV VB VB_UV_DIG VS IRS10752L_STP_IDEAL PARAMS: P_TH_UP={P_VB_UVH} P_TH_DW={P_VB_UVL}
E_VB_UVL VB_UVL 0 VALUE {IF( V(VB,VS) < {P_VB_UVL} , 0.0 , 1.0 )}
R_VB_UVL VB_UVL VB_UVL_LPF {P_R_UV_D_H}
C_VB_UVL VB_UVL_LPF 0 1P
E_VB_UVL_PLS VB_UVL_PLS 0 VALUE {IF( V(VB_UVL_LPF) < 0.5 | V(VB_UV) < 0.5 , 0.0 , 1.0 )}
E_VB_UV VB_UV 0 VALUE {IF( V(VB_UV_DIG) < 0.5 & V(VB_UVL_PLS) < 0.5 , 0.0 , 1.0 )}
X_VCC_UV VCC VCC_UV_DIG COM IRS10752L_STP_IDEAL PARAMS: P_TH_UP={P_VCC_UVH} P_TH_DW={P_VCC_UVL}
E_VCC_UVL VCC_UVL 0 VALUE {IF( V(VCC,COM) < {P_VCC_UVL} , 0.0 , 1.0 )}
R_VCC_UVL VCC_UVL VCC_UVL_LPF {P_R_UV_D_L}
C_VCC_UVL VCC_UVL_LPF 0 1P
E_VCC_UVL_PLS VCC_UVL_PLS 0 VALUE {IF( V(VCC_UVL_LPF) < 0.5 | V(VCC_UV) < 0.5 , 0.0 , 1.0 )}
E_VCC_UV VCC_UV 0 VALUE {IF( V(VCC_UV_DIG) < 0.5 & V(VCC_UVL_PLS) < 0.5 , 0.0 , 1.0 )}
.ENDS IRS10752L_UV_DETECT
.SUBCKT IRS10752L_CC_EMULATOR VCC COM VB VS PARAMS: P_VB_MIN=10 P_VCC_MIN=10 P_IQ_VB=100U P_IQ_VCC=500U P_I_LEAK=1.0U P_V_LEAK=650
G_QB VB VS VALUE {TABLE(V(VB,VS) , 0,0 , 0.1,1U , 1,10U , 0.8*{P_VB_MIN},{P_IQ_VB})}
R_QB VB VS 1E12
G_QCC VCC COM VALUE {TABLE(V(VCC,COM) , 0,0 , 0.1,1U , 1,10U , 0.8*{P_VCC_MIN},{P_IQ_VCC})}
R_QCC VCC COM 1E12
G_LEAK VS COM VALUE {TABLE(V(VB,COM) , 0,0 , {P_V_LEAK},{P_I_LEAK})}
R_LEAK VS COM 1E12
.ENDS IRS10752L_CC_EMULATOR
.SUBCKT IRS10752L_CL_DIO C A PARAMS: P_V_BV=5 P_I_BV=1
G_CL_DIO C A VALUE {TABLE(V(C,A) , 0,0 , {P_V_BV},0 , {P_V_BV}*1.01,{P_I_BV} , 10*{P_V_BV}, 100*{P_I_BV} )}
C_CL_DIO C A 1P
R_CL_DIO C A 1E12
.ENDS IRS10752L_CL_DIO
.SUBCKT IRS10752L_ESD_DIO C A PARAMS: P_V_BV=5 P_I_BV=1
G_CL_DIO C A VALUE {TABLE(V(C,A) , 0,0 , {P_V_BV},0 , {P_V_BV}*1.01,{P_I_BV} , 10*{P_V_BV}, 10*{P_I_BV} )}
C_CL_DIO C A 1P
R_CL_DIO C A 1E12
.ENDS IRS10752L_ESD_DIO
.SUBCKT IRS10752L_RC_DELAY_10 IN OUT PARAMS: P_C_DELAY = 60E-9 P_TH_TPD = 0.5
X_D1 IN OUT IRS10752L_RC_DELAY_5 PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD}
.ENDS IRS10752L_RC_DELAY_10
.SUBCKT IRS10752L_RC_DELAY_5 IN OUT PARAMS: P_C_DELAY = 60E-9 P_TH_TPD = 0.5
X_D1 IN D1 IRS10752L_RC_DELAY_BASE PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD}
X_D2 D1 D2 IRS10752L_RC_DELAY_BASE PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD}
X_D3 D2 D3 IRS10752L_RC_DELAY_BASE PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD}
X_D4 D3 D4 IRS10752L_RC_DELAY_BASE PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD}
X_D5 D4 OUT IRS10752L_RC_DELAY_BASE PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD}
.ENDS IRS10752L_RC_DELAY_5
.SUBCKT IRS10752L_RC_DELAY_BASE IN OUT PARAMS: P_C_DELAY = 60E-9 P_TH_TPD = 0.5
R_DELAY IN IN_DEL 1
C_DELAY IN_DEL 0 {P_C_DELAY}
E_DELAY OUT 0 VALUE={IF( V(IN_DEL) > {P_TH_TPD} , 1.0,0.0 )}
.ENDS IRS10752L_RC_DELAY_BASE
.SUBCKT IRS10752L_ADV_FILTER IN OUT PARAMS: P_C_DELAY = 60E-9 P_TH_TPD = 0.5
R_RISE IN IN_DEL 1
C_RISE IN_DEL 0 {P_C_DELAY}
X_CMP IN_DEL OUT 0 IRS10752L_STP_IDEAL PARAMS: P_TH_UP=0.999 P_TH_DW=0.001
.ENDS IRS10752L_ADV_FILTER
.SUBCKT IRS10752L_STP_IDEAL1 IN OUT GND UP DW PARAMS: P_TH_UP=0.9 P_TH_DW=0.1
E_OUTP OUTP 0 VALUE={IF( V(IN,GND)>=V(UP) | V(OUTN)<0.5 , 1,0 )}
E_OUTN OUTN 0 VALUE={IF( V(IN,GND)<=V(DW) | V(OUTP)<0.5 , 1,0 )}
E_OUT OUT 0 VALUE={V(OUTP)}
.ENDS IRS10752L_STP_IDEAL1
.SUBCKT IRS10752L_STP_IDEAL IN OUT GND PARAMS: P_TH_UP=0.9 P_TH_DW=0.1
E_OUTP OUTP 0 VALUE={IF( V(IN,GND)>={P_TH_UP} | V(OUTN)<0.5 , 1,0 )}
E_OUTN OUTN 0 VALUE={IF( V(IN,GND)<={P_TH_DW} | V(OUTP)<0.5 , 1,0 )}
E_OUT OUT 0 VALUE={V(OUTP)}
.ENDS IRS10752L_STP_IDEAL
.SUBCKT IRS10752L_STN_IDEAL IN OUT GND PARAMS: P_TH_UP=0.9 P_TH_DW=0.1
E_OUTP OUTP 0 VALUE={IF( V(IN,GND)>={P_TH_UP} | V(OUTN)<0.5 , 1,0 )}
E_OUTN OUTN 0 VALUE={IF( V(IN,GND)<={P_TH_DW} | V(OUTP)<0.5 , 1,0 )}
E_OUT OUT 0 VALUE={V(OUTN)}
.ENDS IRS10752L_STN_IDEAL
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