refined implementation
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5a6488535d
commit
03bf92f505
@ -11,13 +11,8 @@
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#define PIN_SWCLK 11
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// open drain emulation, the pin is set with output '0' and is switched between input or output
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// depending on the wanted value, in the high state the line is pulled high by the pull-up and
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// in the low state the line in forced low
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#define OD_PULL(pin, value) gpio_set_dir((pin), (value) ? GPIO_IN : GPIO_OUT)
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// wait time between line transitions
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#define SWD_DELAY() busy_wait_us(1);
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#define SWD_DELAY() busy_wait_us(2);
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// microseconds between each register read/write
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#define STOP_WAIT 8
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@ -25,16 +20,17 @@
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// Single wire debug (SWDIO and SWCLK)
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static inline void ConfigureIOForRVSWD(void)
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{
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// SWDIO, open drain (emulated) with pull-up
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// SWCLK forced, starts at 1
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gpio_init(PIN_SWCLK);
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gpio_set_pulls(PIN_SWCLK, false, false);
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gpio_put(PIN_SWCLK, 1);
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gpio_set_dir(PIN_SWCLK, GPIO_OUT);
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// SWDIO, open drain (emulated) with pull-up
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gpio_init(PIN_SWDIO);
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gpio_set_pulls(PIN_SWDIO, true, false);
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gpio_put(PIN_SWDIO, 0);
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gpio_put(PIN_SWDIO, 1);
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gpio_set_dir(PIN_SWDIO, GPIO_IN);
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gpio_init(PIN_SWCLK);
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gpio_set_pulls(PIN_SWCLK, false, false);
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gpio_put(PIN_SWCLK, 0);
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gpio_set_dir(PIN_SWCLK, GPIO_OUT);
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}
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@ -45,38 +41,12 @@ static inline void ConfigureIOForRVSWIO(void)
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}
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static inline void rvswd_start(void)
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{
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// Start with both lines high
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gpio_put(PIN_SWCLK, 1);
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OD_PULL(PIN_SWDIO, 1);
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//SWD_DELAY();
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// Pull data low
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OD_PULL(PIN_SWDIO, 0);
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SWD_DELAY();
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}
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static inline void rvswd_stop(void)
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{
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gpio_put(PIN_SWCLK, 0);
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SWD_DELAY();
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OD_PULL(PIN_SWDIO, 0);
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SWD_DELAY();
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gpio_put(PIN_SWCLK, 1);
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SWD_DELAY();
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OD_PULL(PIN_SWDIO, 1);
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}
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void rvswd_write_bit(bool value)
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{
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gpio_put(PIN_SWCLK, 0);
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OD_PULL(PIN_SWDIO, value);
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gpio_put(PIN_SWDIO, value);
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gpio_set_dir(PIN_SWDIO, GPIO_OUT);
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gpio_set_dir(PIN_SWDIO, GPIO_IN);
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SWD_DELAY();
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gpio_put(PIN_SWCLK, 1); // Data is sampled on rising edge of clock
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SWD_DELAY();
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@ -85,18 +55,31 @@ void rvswd_write_bit(bool value)
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bool rvswd_read_bit(void)
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{
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OD_PULL(PIN_SWDIO, 0);
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gpio_put(PIN_SWDIO, 1);
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gpio_set_dir(PIN_SWDIO, GPIO_IN);
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gpio_put(PIN_SWCLK, 0);
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OD_PULL(PIN_SWDIO, 1);
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SWD_DELAY();
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bool bit = gpio_get(PIN_SWDIO);
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gpio_put(PIN_SWCLK, 1); // Data is output on rising edge of clock
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SWD_DELAY();
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return bit;
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}
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static inline void rvswd_stop(void)
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{
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gpio_put(PIN_SWCLK, 0);
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SWD_DELAY();
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gpio_put(PIN_SWDIO, 0);
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gpio_set_dir(PIN_SWDIO, GPIO_OUT);
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SWD_DELAY();
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gpio_put(PIN_SWCLK, 1);
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SWD_DELAY();
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gpio_put(PIN_SWDIO, 1);
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gpio_set_dir(PIN_SWDIO, GPIO_IN);
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}
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static void MCFWriteReg32( struct SWIOState * state, uint8_t command, uint32_t value )
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{
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// only supported mode is SWD
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@ -106,35 +89,34 @@ static void MCFWriteReg32( struct SWIOState * state, uint8_t command, uint32_t v
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}
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noInterrupts();
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rvswd_start();
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// start transaction
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gpio_put(PIN_SWDIO, 0);
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gpio_set_dir(PIN_SWDIO, GPIO_OUT);
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SWD_DELAY();
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// ADDR HOST
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bool parity = false; // This time it's odd parity?
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for (uint8_t position = 0; position < 7; position++) {
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bool bit = (command >> (6 - position)) & 1;
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bool parity = true;
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for (uint32_t mask = 1<<6; mask; mask >>= 1) {
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bool bit = !!(command & mask);
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parity ^= bit;
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rvswd_write_bit(bit);
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if (bit) parity = !parity;
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}
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// Operation: write
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rvswd_write_bit(1);
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parity = !parity;
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// Parity bit (even)
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rvswd_write_bit(1); // Operation: write
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rvswd_write_bit(parity);
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rvswd_read_bit(); // ???
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rvswd_read_bit(); // Seems only need to be set for first transaction (We are ignoring that though)
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rvswd_read_bit(); // ???
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rvswd_write_bit(0); // 0 for register, 1 for value.
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rvswd_write_bit(0); // ??? Seems to have something to do with halting.
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// Data
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// DATA
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parity = false; // This time it's even parity?
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for (uint8_t position = 0; position < 32; position++) {
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bool bit = (value >> (31 - position)) & 1;
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for (uint32_t mask = 1<<31; mask; mask >>= 1) {
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bool bit = !!(value & mask);
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parity ^= bit;
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rvswd_write_bit(bit);
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if (bit) parity = !parity;
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}
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// Parity bit
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@ -160,60 +142,55 @@ static int MCFReadReg32( struct SWIOState * state, uint8_t command, uint32_t * v
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return -1;
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}
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bool parity;
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noInterrupts();
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rvswd_start();
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// start transaction
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gpio_put(PIN_SWDIO, 0);
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gpio_set_dir(PIN_SWDIO, GPIO_OUT);
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SWD_DELAY();
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// ADDR HOST
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parity = false;
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for (uint8_t position = 0; position < 7; position++) {
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bool bit = (command >> (6 - position)) & 1;
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bool parity = false;
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for (uint8_t mask = 1<<6; mask; mask >>= 1) {
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bool bit = !!(command & mask);
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parity ^= bit;
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rvswd_write_bit(bit);
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if (bit) parity = !parity;
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}
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// Operation: read
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rvswd_write_bit(0);
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// Parity bit (even)
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rvswd_write_bit(0); // Operation: read
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rvswd_write_bit(parity);
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rvswd_read_bit(); // ??
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rvswd_read_bit(); // ??
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rvswd_read_bit(); // ??
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rvswd_write_bit(0); // 0 for register, 1 for value
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rvswd_write_bit(0); // ??? Seems to have something to do with halting?
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// DATA
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*value = 0;
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// Data
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parity = false;
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uint32_t rval = 0;
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for (uint8_t position = 0; position < 32; position++) {
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bool bit = rvswd_read_bit();
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rval <<= 1;
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if (bit) {
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rval |= 1;
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parity ^= 1;
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}
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rval |= bit;
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parity ^= bit;
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}
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*value = rval;
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// Parity bit
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bool parity_read = rvswd_read_bit();
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if (parity_read != parity) goto read_end;
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rvswd_read_bit(); // ??
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rvswd_read_bit(); // ??
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rvswd_read_bit(); // ??
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rvswd_write_bit(1); // 1 for data
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rvswd_write_bit(1); // 0 for register, 1 for value
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rvswd_write_bit(0); // ??? Seems to have something to do with halting?
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rvswd_stop();
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interrupts();
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read_end:
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interrupts();
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sleep_us(STOP_WAIT);
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return (parity == parity_read) ? 0 : -1;
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}
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