different driver

sim/ZXGD3009DY.asy

@@ -0,0 +1,23 @@
+Version 4
+SymbolType BLOCK
+RECTANGLE Normal -96 -55 96 56
+WINDOW 0 0 -56 Bottom 2
+WINDOW 3 0 56 Top 2
+SYMATTR Prefix X
+SYMATTR Value ZXGD3009DY
+SYMATTR ModelFile ZXGD3009DY.lib
+PIN -96 -32 LEFT 8
+PINATTR PinName VCC
+PINATTR SpiceOrder 1
+PIN -96 0 LEFT 8
+PINATTR PinName IN
+PINATTR SpiceOrder 2
+PIN -96 32 LEFT 8
+PINATTR PinName VEE
+PINATTR SpiceOrder 3
+PIN 96 -32 RIGHT 8
+PINATTR PinName SINK
+PINATTR SpiceOrder 4
+PIN 96 32 RIGHT 8
+PINATTR PinName SOURCE
+PINATTR SpiceOrder 6

sim/ZXGD3009DY.lib

@@ -0,0 +1,52 @@
+* DIODES INCORPORATED AND ITS AFFILIATED COMPANIES AND SUBSIDIARIES (COLLECTIVELY, "DIODES") 
+* PROVIDE THESE SPICE MODELS AND DATA (COLLECTIVELY, THE "SM DATA") "AS IS" AND WITHOUT ANY 
+* REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+* OR FITNESS FOR A PARTICULAR PURPOSE, ANY WARRANTY ARISING FROM COURSE OF DEALING OR COURSE OF 
+* PERFORMANCE, OR ANY WARRANTY THAT ACCESS TO OR OPERATION OF THE SM DATA WILL BE UNINTERRUPTED, 
+* OR THAT THE SM DATA OR ANY SIMULATION USING THE SM DATA WILL BE ERROR FREE. TO THE MAXIMUM 
+* EXTENT PERMITTED BY LAW, IN NO EVENT WILL DIODES BE LIABLE FOR ANY DIRECT OR INDIRECT, 
+* SPECIAL, INCIDENTAL, PUNITIVE OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH 
+* THE PRODUCTION OR USE OF SM DATA, HOWEVER CAUSED AND UNDER WHATEVER CAUSE OF ACTION OR THEORY 
+* OF LIABILITY BROUGHT (INCLUDING, WITHOUT LIMITATION, UNDER ANY CONTRACT, NEGLIGENCE OR OTHER 
+* TORT THEORY OF LIABILITY), EVEN IF DIODES HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, 
+* AND DIODES' TOTAL LIABILITY (WHETHER IN CONTRACT, TORT OR OTHERWISE) WITH REGARD TO THE SM 
+* DATA WILL NOT, IN THE AGGREGATE, EXCEED ANY SUMS PAID BY YOU TO DIODES FOR THE SM DATA.
+
+
+
+*DIODES_INC_SPICE_MODEL
+*SIMULATOR=SIMETRIX
+*ORIGIN=DZSL_DPG_SU
+*DATE=29Jul2016
+*VERSION=1
+
+** PIN ORDER 1=Vcc 2=IN 3=Vee 4=SINK 5=NC 6=SOURCE
+.SUBCKT ZXGD3009DY 1 2 3 4 5 6
+Q1 10 2 60 N
+Q2 30 2 40 P
+L1 1 10 1p
+L2 3 30 1p
+L3 4 40 100p
+L4 6 60 100p
+.MODEL N NPN(IS=6E-14 BF=500 NF=.98 ISE=1E-14 NE=1.25 ISC=3.3E-14 BR=15 NR=1 NC=1.12 CJE=36.592p VJE=.75 MJE=.37 CJC=9.674p VJC=.5 MJC=.33 VAF=28 IKF=1 RC=.1 RE=.05 NK=.808)
+.MODEL P PNP IS=20e-14 NF=1 ISE=5e-15 NE=1.3 BF=350
++ VAF=26 IKF=1 ISC=9e-15 NC=1.03 BR=15 NR=1 VAR=5.7 IKR=0.6 RE=0.067
++ RB=0.33 RC=0.012 CJE=36.99e-12 VJE=0.75 MJE=0.41 CJC=13.96e-12 VJC=0.5
++ MJC=0.33 TF=8e-10 TR=5.6e-9 QUASIMOD=1 RCO=0.66 GAMMA=1.3e-9 NK=.71
++ XTB=1.5 TRE1=0.004 TRB1=0.003 TRC1=0.004
+.ENDS
+
+*                (c)  2016 Diodes Inc
+*
+*   The copyright in these models  and  the designs embodied belong
+*   to Diodes Incorporated (" Zetex ").  They  are  supplied
+*   free of charge by Zetex for the purpose of research and design
+*   and may be used or copied intact  (including this notice)  for
+*   that purpose only.  All other rights are reserved.  The models
+*   are believed accurate but no condition  or warranty  as to their
+*   merchantability or fitness for purpose is given and no liability
+*   in respect of any use is accepted by Diodes Incorporated, its distributors
+*   or agents.
+*
+*   Diodes Zetex Semiconductors Ltd, Zetex Technology Park, Chadderton,
+*   Oldham, United Kingdom, OL9 9LL

sim/pi_filter.asc

@@ -6,8 +6,8 @@ WIRE -960 -560 -1168 -560
 WIRE -832 -560 -960 -560
 WIRE -384 -560 -832 -560
 WIRE 128 -560 -384 -560
-WIRE 272 -560 128 -560
+WIRE 240 -560 128 -560
-WIRE 528 -560 272 -560
+WIRE 528 -560 240 -560
 WIRE 752 -560 528 -560
 WIRE -1360 -544 -1360 -560
 WIRE -960 -544 -960 -560
@@ -22,23 +22,23 @@ WIRE -1600 -432 -1680 -432
 WIRE 528 -416 528 -448
 WIRE -1600 -400 -1600 -432
 WIRE -1680 -336 -1680 -432
-WIRE 272 -336 272 -560
+WIRE 240 -336 240 -560
-WIRE 288 -336 272 -336
+WIRE 256 -336 240 -336
-WIRE 480 -320 464 -320
+WIRE 464 -336 448 -336
 WIRE 752 -320 752 -560
 WIRE 128 -304 128 -432
-WIRE 288 -304 128 -304
+WIRE 256 -304 128 -304
-WIRE 480 -304 480 -320
+WIRE 464 -304 464 -336
 WIRE 528 -304 528 -352
-WIRE 528 -304 480 -304
+WIRE 528 -304 464 -304
 WIRE 672 -304 528 -304
 WIRE 704 -304 672 -304
 WIRE -1600 -288 -1600 -320
-WIRE 480 -288 480 -304
+WIRE 256 -272 240 -272
-WIRE 480 -288 464 -288
+WIRE 464 -272 464 -304
-WIRE 288 -272 272 -272
+WIRE 464 -272 448 -272
 WIRE -1680 -240 -1680 -272
-WIRE 272 -208 272 -272
+WIRE 240 -208 240 -272
 WIRE -1600 -112 -1600 -208
 WIRE -1600 -64 -1600 -112
 WIRE 128 -64 128 -304
@@ -82,7 +82,7 @@ FLAG 992 496 0
 FLAG -1680 -240 0
 FLAG 752 0 tip
 FLAG 672 -304 gate
-FLAG 272 -208 0
+FLAG 240 -208 0
 SYMBOL res 736 336 R0
 SYMATTR InstName R1
 SYMATTR Value {rtip}
@@ -169,13 +169,13 @@ WINDOW 0 24 64 Left 2
 WINDOW 3 24 0 Left 2
 SYMATTR InstName D2
 SYMATTR Value EDZV15B
-SYMBOL ZXGD3006 368 -304 R0
+SYMBOL ZXGD3009DY 352 -304 R0
 SYMATTR InstName U1
 TEXT -1656 -1016 Left 2 !.tran 30m
-TEXT -1648 -808 Left 2 !.param fsw=1k
+TEXT -1648 -808 Left 2 !.param fsw=3k
 TEXT -1648 -776 Left 2 !.param d={pout/(vbus*vbus/rtip)}
 TEXT -1648 -904 Left 2 !.param vbus=28
 TEXT -1648 -840 Left 2 !.param pout=130
 TEXT -1648 -872 Left 2 !.param rtip=2.5
 TEXT -1648 -936 Left 2 !.param vcc=3.3
-TEXT 312 -208 Left 2 !.lib ZXGD3006E6.lib
+TEXT 272 -208 Left 2 !.lib ZXGD3009DY.lib