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190 lines
7.1 KiB
190 lines
7.1 KiB
#ifndef _PLATFORM_CLOCK_H
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#define _PLATFORM_CLOCK_H
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#include <stdint.h>
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#include <macro.h>
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/* Clocking and reset is managed by the PRCI (Power Reset Clocking Interrupt)
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* block (Figure 24) [77]
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*
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* FU740-C000 generates all internal clocks from 26 MHz hfclk driven from an
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* external oscillator (HFCLKIN) or crystal (HFOSCIN) input, selected by input
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* HFXSEL. All harts operate in a single clock domain (coreclk) supplied by
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* either corepll or dvfscorepll, which can be selected using the corepllsel
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* register. These PLLs step 26 MHz hfclk up to higher frequencies.
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* The recommended frequency of coreclk is 1.0GHz, however operation at up to
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* 1.5GHz is possible.
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* tlclk is a divided version of the coreclk and generates the clock for the L2
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* cache.
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* The hfpclkpll generates the clock for peripherals such as SPI, UART, GPIO,
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* I2C, and PWM.
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* dvfs_core_pll enables the user to change the CPU frequency without dropping
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* down to the lower frequency hfclk.
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* The DDR, Ethernet and PCIe Subsystems operate asynchronously.
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* The PRCI contains two dedicated PLLs used to step 26 MHz hfclk up to the DDR
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* and Ethernet operating frequencies.
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* The PCIe Subsystem contains its own clock generation.
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* The PRCI contains memory-mapped registers that control the clock selection
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* and configuration of the PLLs.
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* On power-on, the default PRCI register settings start the harts running
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* directly from hfclk.
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* All additional clock management, for instance initializing the DDR PLL or
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* stepping the coreclk frequency, is performed through software reads and
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* writes to the memory-mapped PRCI control registers.
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* The CPU real time clock (rtcclk) runs at 1 MHz and is driven from input pin
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* RTCCLKIN. This should be connected to an external oscillator.
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* JTAG debug logic runs off of JTAG TCK as described in Chapter 26.
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*
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* Reset
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* The FU740-C000 has two external reset pins.
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* PORESET_N is an asynchonous active low power-on reset that should be
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* connected to an external power sequencing/supervisory circuit. ERESET_N is
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* an asynchonous active low reset that can be connected to a reset button.
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* There is internal debounce and stretch logic. The PRCI also contains hardware
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* to generate internal synchronous resets for coreclk, tlclk, and hfpclk
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* domains and handle reset to and from the debug module. Resets for the DDR,
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* Eth- ernet and PCIE Subsystems are performed through software reads and
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* writes to memory-mapped PRCI control registers. These registers are outlined
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* in Table 34 below.
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*/
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/* Table 21: PRCI Memory Map
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* Offset Name Description
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* 0x00 hfxosccfg Crystal Oscillator Configuration and Status
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* 0x04 core_pllcfg PLL Configuration and Status
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* 0x08 core_plloutdiv PLL Final Divide Configuration
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* 0x0C ddr_pllcfg PLL Configuration and Status
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* 0x10 ddr_plloutdiv PLL Final Divide Configuration
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* 0x1C gemgxl_pllcfg PLL Configuration and Status
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* 0x20 gemgxl_plloutdiv PLL Final Divide Configuration
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* 0x24 core_clk_sel_reg Select core clock source. 0: coreclkpll 1: external hfclk
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* 0x28 devices_reset_n Software controlled resets (active low)
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* 0x2C clk_mux_status Current selection of each clock mux
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* 0x38 dvfs_core_pllcfg PLL Configuration and Status
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* 0x3C dvfs_core_plloutdiv PLL Final Divide Configuration
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* 0x40 corepllsel Select which PLL output to use for core clock. 0: corepll 1: dvfscorepll
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* 0x50 hfpclk_pllcfg PLL Configuration and Status
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* 0x54 hfpclk_plloutdiv PLL Final Divide Configuration
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* 0x58 hfpclkpllsel Select source for Periphery Clock (pclk). 0: hfpclkpll 1: external hfclk
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* 0x5C hfpclk_div_reg HFPCLK PLL divider value
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* 0xE0 prci_plls Indicates presence of each PLL
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*/
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#define HFCLK_FREQ_HZ 26000000L
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#define PRCI_MEMORY_BLOCK 0x10000000L
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struct S_PACKED prci_pllcfg {
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uint32_t pllr:6; // [RW, 0x1] PLL R Value
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uint32_t pllf:9; // [RW, 0x1F] PLL F Value
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uint32_t pllq:3; // [RW, 0x3] PLL Q Value
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uint32_t pllrange:3; // [RW, 0x0] PLL Range Value
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uint32_t reserved0:3;
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uint32_t pllbypass:1; // [RW, 0x1] PLL Bypass
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uint32_t pllfsebypass:1; // [RW, 0x1] PLL FSE Bypass
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uint32_t reserved1:5;
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uint32_t plllock:1; // [RO, X] PLL Lock
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};
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struct S_PACKED prci_plloutdiv {
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uint32_t reserved:31;
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uint32_t pllcke:1; // [RW, 0x0] PLL Clock Enable
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};
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struct S_PACKED prci_mem_map {
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// Offset 0x0
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struct prci_hfxosccfg {
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uint32_t reserved:30;
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uint32_t hfxoscen:1; // [RW, 0x1] Crystal Oscillator Enable
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uint32_t hfxoscrdy:1; // [RO, X] Crystal Oscillator Ready
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} hfxosccfg;
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// Offset 0x4
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struct prci_pllcfg core_pllcfg;
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// Offset 0x8
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struct { uint32_t reserved; } core_plloutdiv;
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// Offset 0xC
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struct prci_pllcfg ddr_pllcfg;
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// Offset 0x10
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struct prci_plloutdiv ddr_plloutdiv;
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uint8_t off0[8];
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// Offset 0x1C
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struct prci_pllcfg gemgxl_pllcfg;
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// Offset 0x20
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struct prci_plloutdiv gemgxl_plloutdiv;
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// Offset 0x24
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uint32_t core_clk_sel_reg;
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// Offset 0x28
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struct prci_devices_reset_n {
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uint32_t ddrctrl_reset_n:1; // [RW, 0x0] Active-Low ddrctrl reset
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uint32_t ddraxi_reset_n:1; // [RW, 0x0] Active-Low ddraxi reset
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uint32_t ddrahb_reset_n:1; // [RW, 0x0] Active-Low ddrahb reset
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uint32_t ddrphy_reset_n:1; // [RW, 0x0] Active-Low ddrphy reset
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uint32_t pcieaux_reset_n:1; // [RW, 0x0] Active-Low pcieaux reset
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uint32_t gemgxl_reset_n:1; // [RW, 0x0] Active-Low gemgxl reset
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uint32_t reserved:26;
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} devices_reset_n;
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// Offset 0x2C
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struct prci_clk_mux_status {
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uint32_t coreclkpllsel:1; // [RO, X] Current setting of coreclkpllsel mux
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uint32_t tlclksel:1; // [RO, X] Current setting of tlclksel mux
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uint32_t rtcxsel:1; // [RO, X] Current setting of rtcxsel mux
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uint32_t ddrctrlclksel:1; // [RO, X] Current setting of ddrctrlclksel mux
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uint32_t ddrphyclksel:1; // [RO, X] Current setting of ddrphyclksel mux
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uint32_t reserved0:1; // [RO, X] Current setting of reserved0 mux
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uint32_t gemgxlclksel:1; // [RO, X] Current setting of gemgxlclksel mux
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uint32_t mainmemclksel:1; // [RO, X] Current setting of mainmemclksel mux
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uint32_t reserved:24;
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} clk_mux_status;
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uint8_t off1[8];
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// Offset 0x38
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struct prci_pllcfg dvfs_core_pllcfg;
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// Offset 0x3C
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struct prci_plloutdiv dvfs_core_plloutdiv;
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// Offset 0x40
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uint32_t corepllsel;
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uint8_t off2[12];
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// Offset 0x50
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struct prci_pllcfg hfpclk_pllcfg;
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// Offset 0x54
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struct prci_plloutdiv hfpclk_plloutdiv;
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// Offset 0x58
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uint32_t hfpclkpllsel;
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// Offset 0x5C
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uint32_t hfpclk_div_reg; // [RW, 0x0] HFPCLK PLL divider value
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uint8_t off3[128];
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// Offset 0xE0
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struct prci_prci_plls {
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uint32_t cltxpll:1; // [RO, X] Indicates presence of cltxpll
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uint32_t gemgxlpll:1; // [RO, X] Indicates presence of gemgxlpll
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uint32_t ddrpll:1; // [RO, X] Indicates presence of ddrpll
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uint32_t hfpclkpll:1; // [RO, X] Indicates presence of hfpclkpll
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uint32_t dvfscorepll:1; // [RO, X] Indicates presence of dvfscorepll
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uint32_t corepll:1; // [RO, X] Indicates presence of corepll
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uint32_t reserved:26;
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} prci_plls;
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};
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static_assert((sizeof(struct prci_mem_map) == 0xE4),
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"prci_mem_map is not the right size");
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#endif |