1
Sub
Bits
32
And
Bits
32
wideShape
true
Or
Bits
32
wideShape
true
XOr
Bits
32
wideShape
true
In
Label
a
Bits
32
In
Label
b
Bits
32
multiply-add.dig
In
Label
c
Bits
32
Neg
Bits
32
Out
Label
Z
Splitter
Input Splitting
32
Output Splitting
31,1
Out
Label
N
Add
Bits
32
XOr
wideShape
true
Out
Label
V
Multiplexer
Selector Bits
3
Bits
32
Multiplexer
Selector Bits
3
Const
Value
0
Out
Label
u0
Bits
32
Out
Label
u1
Bits
32
Out
Label
C_o
Tunnel
NetName
sel
Tunnel
NetName
sel
In
Label
C_i
Splitter
rotation
Input Splitting
32
Output Splitting
31,1
Splitter
rotation
Input Splitting
32
Output Splitting
31,1
Splitter
Input Splitting
32
Output Splitting
5
And
wideShape
true
XNOr
rotation
wideShape
true
And
wideShape
true
nor32.dig
nor32.dig
shift32.dig
Text
Description
ALU Opcode
0000 -> ADD
0001 -> SUB
0010 -> MAD
0011 -> MADS
0100 -> AND
0101 -> OR
0110 -> XOR
0111 -> NEG
1000 -> LSL
1001 -> LSR
1010 -> SCL
1011 -> SCR
1100 -> ROL
1101 -> ROR
1110 -> ASR
1111 -> NOP
In
Label
OP
Bits
4
Splitter
Input Splitting
4
Output Splitting
1*4
And
inverterConfig
In_1
In_2
Inputs
4
Tunnel
NetName
mad_s
Splitter
Input Splitting
1*3
Output Splitting
3
Tunnel
NetName
shift_op
Tunnel
rotation
NetName
shift_op
Tunnel
rotation
NetName
mad_s
And
inverterConfig
In_1
In_2
Inputs
3
Tunnel
NetName
long_z
Multiplexer
Tunnel
NetName
long_z
And
And
Or
Inputs
3
Splitter
Input Splitting
1*3
Output Splitting
3
And
And
inverterConfig
In_2
In_3
Inputs
3
And
inverterConfig
In_1
In_2
Inputs
3
Or
Inputs
4
And
inverterConfig
In_1
In_2
Inputs
3
And
inverterConfig
In_1
In_3
Inputs
3
Or
Inputs
3
Tunnel
NetName
sel