From c336ca328f97df3ca194ac428d4ec3788eeb049f Mon Sep 17 00:00:00 2001 From: Alessandro Mauri Date: Sat, 29 Oct 2022 23:29:17 +0200 Subject: [PATCH] Sat Oct 29 11:29:17 PM CEST 2022 --- INSTRUCTIONS.md | 15 +++++++++++++ alu.dig | 12 ++--------- registers.dig | 56 ++++++++++++++++++++++++++++++------------------- 3 files changed, 52 insertions(+), 31 deletions(-) create mode 100644 INSTRUCTIONS.md diff --git a/INSTRUCTIONS.md b/INSTRUCTIONS.md new file mode 100644 index 0000000..bc6d726 --- /dev/null +++ b/INSTRUCTIONS.md @@ -0,0 +1,15 @@ +# RISC combined instruction set + +goal: a semi-efficient insatruction set that offers few instructions that offer +the combined functions of conventional risc instuctions. + +as such most instructions could be pipelined, I don't know how to feel about that + +| mnemonic | function | opcode | +|------------|----------------|--------| +| Arithmetic | | | +|------------|----------------|--------| +| Memory | | | +|------------|----------------|--------| +| LD Rd, Ra:Rb| +| ST | diff --git a/alu.dig b/alu.dig index b32a592..99aea1f 100644 --- a/alu.dig +++ b/alu.dig @@ -11,24 +11,16 @@ Add - - Label - ADD/C - Bits 16 - + Sub - - Label - SUB/C - Bits 16 @@ -39,7 +31,7 @@ signed_mul.dig - + diff --git a/registers.dig b/registers.dig index 041f198..c43af62 100644 --- a/registers.dig +++ b/registers.dig @@ -466,7 +466,7 @@ Label - RE + W @@ -528,7 +528,7 @@ Label - Rd + Ra Bits @@ -542,7 +542,7 @@ Label - Rr + Rb Bits @@ -556,24 +556,24 @@ Label - DS + Sa Bits 5 - + Tunnel NetName - ds + sa - + Tunnel @@ -584,7 +584,7 @@ NetName - ds + sa @@ -594,24 +594,24 @@ Label - RS + Sb Bits 5 - + Tunnel NetName - rs + sb - + Tunnel @@ -622,11 +622,25 @@ NetName - rs + sb + + In + + + Label + Sw + + + Bits + 5 + + + + @@ -693,6 +707,10 @@ + + + + @@ -821,10 +839,6 @@ - - - - @@ -1173,10 +1187,6 @@ - - - - @@ -1393,6 +1403,10 @@ + + + +